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fujitsu semiconductor data sheet copyright?2004-2010 fujitsu semiconductor limited all rights reserved 2010.7 for the information for microcontrolle r supports, see the following web site. this web site includes the "customer design review supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ 16-bit microcontroller cmos f 2 mc-16lx mb90330a series mb90333a/f334a/f335a/v330a description the mb90330a series are 16-bit microcontrollers designed for applications, such as personal computer peripheral devices, that require usb communications. the usb feat ure supports not only 12-mbps function operation but also host operation. it is equipped wi th functions that are suitable for personal computer peripheral devices such as displays and audio devices, and control of mobile devices that support usb communications. while inheriting the at architecture of the f 2 mc family, the instruction set supports the c language and extended addressing modes and contains enhanced signed multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. in addition, long word processing is now available by intro- ducing a 32-bit accumulator. note : f 2 mc is the abbreviation of fuji tsu flexible microcontroller. features ? clock ? built-in oscillation circuit and pll clock frequency multiplication circuit ? oscillation clock ? the main clock is the oscillation clock divi ded into 2 (for oscillation 6 mhz : 3 mhz) ? clock for usb is 48 mhz ? machine clock frequency of 6 mhz, 12 mhz, or 24 mhz selectable ? minimum execution time of instruction : 41.7 ns (6 mhz oscillation clock, 4-time multiplied : machine clock 24 mhz and at operating v cc = 3.3 v). ? the maximum memory space : 16 mbytes ? 24-bit addressing (continued) ds07-13734-9e
mb90330a series 2 ds07-13734-9e (continued) ? bank addressing ? instruction system ? data types : bit, byte, word and long word ? addressing mode (23 types) ? enhanced high-precision computing with 32-bit accumulator ? enhanced multiply/divide instructions with sign and the reti instruction ? instruction system compatible with high-le vel language (c language) and multi-task ? employing system stack pointer ? instruction set symmetry and barrel shift instructions ? program patch function (2 address pointer) ? 4-byte instruction queue ? interrupt function ? priority levels are programmable ? 32 interrupts function ? data transfer function ? extended intelligent i/o service function (ei 2 os) : maximum of 16 channels ? dmac : maximum 16 channels ? low power consumption mode ? sleep mode (with the cpu operating clock stopped) ? time-base timer mode (with the oscillato r clock and time-base timer operating) ? stop mode (with the oscillator clock stopped) ? cpu intermittent operation m ode (with the cpu operating at fixed intervals of set cycles) ? watch mode (with 32 khz oscillator clock and watch timer operating) ? package ? lqfp-120p (fpt-120p-m24 : 0.40 mm pin pitch) ? lqfp-120p (fpt-120p-m21 : 0.50 mm pin pitch) ? process : cmos technology ? operation guaranteed temperature : ? 40 c to + 85 c (0 c to + 70 c when usb is in use)
mb90330a series ds07-13734-9e 3 internal peripheral function (resource) ? i/o port : max 94 ports ? time-base timer : 1 channel ? watchdog timer : 1 channel ? watch timer : 1 channel ? 16-bit reload timer : 3 channels ? multi-functional timer ? 16-bit free run timer : 1 channel ? output compare : 4 channels an interrupt request can be output when the 16-bit fr ee-run timer value matches the compare register value. ? input capture : 4 channels upon detection of the effective edge of the signal input to the external inpu t pin, the input capture unit sets the input capture data register to the 16-bit free-r un timer value to output an interrupt request. ? 8/16-bit ppg timer (8-bit 6 channels or 16-bit 3 channels) the period and duty of the output pulse can be set by the program. ? 16-bit pwc timer : 1 channel timer function and pulse width measurement function ? uart : 4 channels ? full-duplex double buffer (8-bit length) ? asynchronous transfer or clock-synchronous serial (extended i/o serial) transfer can be set. ? extended i/o serial interface : 1 channel ? dtp/external interrupt circuit (8 channels) ? activate the extended intelligent i/o se rvice by external interrupt input ? interrupt output by external interrupt input ? delay interrupt output module ? output an interrupt request for task switching ? 8/10-bit a/d converter : 16 channels ? 8-bit resolution or 10-bit resolution can be set. ? usb : 1 channel ? usb function (correspond to usb full speed) ? full speed is supported/endpoint are specifiable up to six. ? dual port ram (the fifo mode is supported). ? transfer type : control, interrupt, bulk, or isochronous transfer possible ? usb host function ? i 2 c interface : 3 channels ? supports intel sm bus standard and phillips i 2 c bus standards ? two-wire data transfer protocol specification ? master and slave transmission/reception
mb90330a series 4 ds07-13734-9e product lineup * : it is setting of jumper switch (tool vcc) when emulator (mb2147- 01) is used. please refer to the mb2147-01 or mb2147-20 hardware manual (3.3 emulato r-dedicated power supply switching) about details. part number MB90V330A mb90f334a mb90f335a mb90333a type for evaluation built-in flash memory built-in flash memory built-in mask rom rom capacity no 384 kbytes 512 kbytes 256 kbytes ram capacity 28 kbytes 24 kbytes 30 kbytes 16 kbytes emulator-specific power supply * yes ? cpu functions number of basic instructions : 351 instructions minimum instruction execution time : 41.7 ns/at oscillation of 6 mhz (when 4 times are used : machine clock of 24 mhz) addressing type : 23 types program patch function : for 2 address pointers maximum memory space : 16 mbytes ports i/o ports (cmos) 94 ports uart equipped with full-duplex double buffer clock synchronous or asynchronous operation selectable it can also be used for i/o serial built-in special baud-rate generator built-in 4 channels 16-bit reload timer 16-bit reload timer operation built-in 3 channels multi-functional timer 16-bit free run timer 1 channel output compare 4 channels input capture 4 channels 8/16-bit ppg timer (8-bit mode 6 channels, 16-bit mode 3 channels) 16-bit pwc timer 1 channel 8/10-bit a/d converter 16 channels (input multiplex) 8-bit resolution or 10-bit resolution can be set. conversion time : 7.16 s at minimum (24 mhz machine clock at maximum) dtp/external interrupt 8 channels interrupt factor : ?l? ?h? edge/?h? ?l? edge/?l? level/?h? level selectable i 2 c 3 channels extended i/o serial interface 1 channel usb 1 channel usb function (correspond to usb full speed) usb host function external bus interface for multi-bus/non-multi-bus withstand voltage of 5 v 16 ports (excluding utest and i/o for i 2 c) low power consumption mode sleep mode/time-base timer mode/s top mode/cpu intermittent mode/ watch mode process cmos operating voltage 3.3 v 0.3 v (at maximum machine clock 24 mhz)
mb90330a series ds07-13734-9e 5 packages and product models : yes : no note : for detailed information on each package, refer to ? package dimensions?. package mb90333a mb90f334a mb90f335a MB90V330A fpt-120p-m24 (lqfp-0.40 mm) fpt-120p-m21 (lqfp-0.50 mm) pga-299c-a01 (pga)
mb90330a series 6 ds07-13734-9e pin assignment (top view) (fpt-120p-m24 / fpt-120p-m21) p30/a00/tin1 p31/a01/tot1 p32/a02/tin2 p33/a03/tot2 p34/a04 p35/a05 p36/a06 p37/a07 p40/a08/tin0 p41/a09/tot0 p42/a10/sin0 p43/a11/sot0 x0a x1a v cc v ss p44/a12/sck0 p45/a13/sin1 p46/a14/sot1 p47/a15/sck1 p60/int0 p61/int1 p62/int2/sin p63/int3/sot p64/int4/sck p65/int5/pwc p66/int6/scl0 p67/int7/sda0 p90/sin2 p91/sot2 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 p27/a23/ppg3 p26/a22/ppg2 p25/a21/ppg1 p24/a20/ppg0 p23/a19 p22/a18 p21/a17 p20/a16 p17/ad15/d15 p16/ad14/d14 p15/ad13/d13 p14/ad12/d12 x0 x1 v ss v cc p13/ad11/d11 p12/ad10/d10 p11/ad09/d09 p10/ad08/d08 p07/ad07/d07 p06/ad06/d06 p05/ad05/d05 p04/ad04/d04 p03/ad03/d03 p02/ad02/d02 p01/ad01/d01 p00/ad00/d00 p57/clk p56/rdy 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 p92/sck2 p93/sin3 p94/sot3 p95/sck3 p96/adtg/frck av cc avrh av ss p70/an0 p71/an1 p72/an2 p73/an3 p74/an4 p75/an5 p76/an6 p77/an7 v ss p80/an8 p81/an9 p82/an10 p83/an11 p84/an12 p85/an13 p86/an14 p87/an15 pa0/in0 pa1/in1 pa2/in2 pa3/in3 pa4/out0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 rst md0 md1 md2 p55/hak p54/hrq p53/wrh p52/wrl p51/rd p50/ale hcon v cc hvp hvm v ss v cc dvp dvm v ss utest pb6/ppg5 pb5/ppg4 pb4 pb3/sda2 pb2/scl2 pb1/sda1 pb0/scl1 pa7/out3 pa6/out2 pa5/out1
mb90330a series ds07-13734-9e 7 pin description (continued) pin no. pin name i/o circuit type* function 108, 107 x0, x1 a terminals to connect the oscillator. when connecting an external clock, leave the x1 pin side unconnected. 13, 14 x0a, x1a a 32 khz oscillation terminals. 90 rst f external reset input pin. 93 to 100 p00 to p07 h general purpose input/output port. the ports can be set to be added with a pull-up resistor (rd00 to rd07 = 1) by the pull-up resistor setting regist er (rdr0). (when the power output is set, it is invalid.) ad00 to ad07 function as an i/o pin for the low-or der external address and data bus in multiplex mode. d00 to d07 function as an output pin for the low-order external data bus in non- multiplex mode. 101 to 104 p10 to p13 h general purpose input/output port. the ports can be set to be added with a pull-up resistor (rd10 to rd13 = 1) by the pull-up resistor setting regist er (rdr1). (when the power output is set, it is invalid.) ad08 to ad11 function as an i/o pin for the high-or der external address and data bus in multiplex mode. d08 to d11 function as an output pin for the hi gh-order external data bus in non- multiplex mode. 109 to 112 p14 to p17 h general purpose input/output port. the ports can be set to be added with a pull-up resistor (rd14 to rd17 = 1) by the pull-up resistor setting regist er (rdr1). (when the power output is set, it is invalid.) ad12 to d15 function as an i/o pin for the high-or der external address and data bus in multiplex mode. d12 to d15 function as an output pin for the hi gh-order external data bus in non- multiplex mode. 113 to 116 p20 to p23 d this is a general purpose i/o port. when the bits of external address output control register (hacr) are set to ?1 ? in external bus mode, these pins function as general purpose i/o ports. a16 to a19 when the bits of external address output control register (hacr) are set to ?0? in multiplex mode, t hese pins function as addr ess high output pins. when the bits of external address output control register (hacr) are set to ?0? in non-multiplex mode, these pins function as address high output pins.
mb90330a series 8 ds07-13734-9e (continued) pin no. pin name i/o circuit type* function 117 to 120 p24 to p27 d this is a general purpose i/o port. when the bits of external address output control register (hacr) are se t to ?1? in external bus mode, these pins function as general purpose i/o ports. a20 to a23 when the bits of external address ou tput control register (hacr) are set to ?0? in multiplex mode, these pins function as address high output pins. when the bits of external address ou tput control register (hacr) are set to ?0? in non-multiplex mode, these pins function as address high output pins. ppg0 to ppg3 function as ch.0 to ch.3 output pins for the 8-bit ppg timer. 1 p30 d general purpose input/output port. a00 function as the external addre ss pin in non-multi-bus mode. tin1 function as an event input pi n for 16-bit reload timer ch.1. 2 p31 d general purpose input/output port. a01 function as the external addre ss pin in non-multi-bus mode. tot1 function as the output pin for 16-bit reload timer ch.1. 3 p32 d general purpose input/output port. a02 function as the external addre ss pin in non-multi-bus mode. tin2 function as an event input pi n for 16-bit reload timer ch.2. 4 p33 d general purpose input/output port. a03 function as the external addre ss pin in non-multi-bus mode. tot2 function as the output pin for 16-bit reload timer ch.2. 5 to 8 p34 to p37 d general purpose input/output port. a04 to a07 function as the external address pin in non-multi-bus mode. 9 p40 g general purpose input/output port. a08 function as the external addre ss pin in non-multi-bus mode. tin0 function as an event input pi n for 16-bit reload timer ch.0. 10 p41 g general purpose input/output port. a09 function as the external addre ss pin in non-multi-bus mode. tot0 function as the output pin for 16-bit reload timer ch.0. 11 p42 g general purpose input/output port. a10 function as the external addre ss pin in non-multi-bus mode. sin0 function as a data input pin for uart ch.0. 12 p43 g general purpose input/output port. a11 function as the external addre ss pin in non-multi-bus mode. sot0 function as a data output pin for uart ch.0. 17 p44 g general purpose input/output port. a12 function as the external addre ss pin in non-multi-bus mode. sck0 function as a clock i/o pin for uart ch.0.
mb90330a series ds07-13734-9e 9 (continued) pin no. pin name i/o circuit type* function 18 p45 g general purpose input/output port. a13 function as the external address pin in non-multi-bus mode. sin1 function as a data input pin for uart ch.1. 19 p46 g general purpose input/output port. a14 function as the external address pin in non-multi-bus mode. sot1 function as a data output pin for uart ch.1. 20 p47 g general purpose input/output port. a15 function as the external address pin in non-multi-bus mode. sck1 function as a clock i/o pin for uart ch.1. 81 p50 l general purpose input/output port. ale function as the address latch e nable signal pin in external bus mode. 82 p51 l general purpose input/output port. rd function as the read strobe outp ut pin in external bus mode. 83 p52 l general purpose input/output port. wrl function as the data write strobe out put pin on the lower side in external bus mode. this pin functions as a general-purpose i/o port when the wre bit in the epcr register is ?0?. 84 p53 l general purpose input/output port. wrh function as the data write strobe outp ut pin on the higher side in bus width 16-bit external bus mode. this pin f unctions as a general-purpose i/o port when the wre bit in the epcr register is ?0?. 85 p54 l general purpose input/output port. hrq function as the hold request input pin in external bus mode. this pin functions as a general-purpose i/o port when the hde bit in the epcr register is ?0?. 86 p55 l general purpose input/output port. hak function as the hold acknowledge outpu t pin in external bus mode. this pin functions as a general-purpose i/o port when the hde bit in the epcr register is ?0?. 91 p56 l general purpose input/output port. rdy function as the external ready input pin in external bus mode. this pin functions as a general-purpose i/o port when the rye bit in the epcr register is ?0?. 92 p57 l general purpose input/output port. clk function as the machine cycle clock out put pin in external bus mode. this pin functions as a general-purpose i/o port when the cke bit in the epcr register is ?0?. 21, 22 p60, p61 c general purpose input/output port. (with stand voltage of 5 v) int0, int1 function as external in terrupt ch.0 and ch.1 input pins.
mb90330a series 10 ds07-13734-9e (continued) pin no. pin name i/o circuit type* function 23 p62 c general purpose input/output port s. (withstand voltage of 5 v) int2 function as an external interrupt ch.2 input pin. sin extended i/o serial interface data input pin. 24 p63 c general purpose input/output port . (withstand voltage of 5 v) int3 function as an external interrupt ch.3 input pin. sot extended i/o serial interface data output pin. 25 p64 c general purpose input/output port . (withstand voltage of 5 v) int4 function as an external interrupt ch.4 input pin. sck extended i/o serial interface clock input/output pin. 26 p65 c general purpose input/output port . (withstand voltage of 5 v) int5 function as an external interrupt ch.5 input pin. pwc function as the pwc input pin. 27 p66 c general purpose input/output port . (withstand voltage of 5 v) int6 function as an external interrupt ch.6 input pin. scl0 function as the ch.0 clock i/o pin for the i 2 c interface. set port output to high-z during i 2 c interface operations. 28 p67 c general purpose input/output port . (withstand voltage of 5 v) int7 function as an external interrupt ch.7 input pin. sda0 function as the ch.0 data i/o pin for the i 2 c interface. set port output to high-z during i 2 c interface operations. 39 to 46 p70 to p77 i general purpose input/output port. an0 to an7 function as input pins for analog ch.0 to ch.7. 48 to 55 p80 to p87 i general purpose input/output port. an8 to an15 function as input pi ns for analog ch.8 to ch.15. 29 p90 d general purpose input/output port. sin2 function as a data input pin for uart ch.2. 30 p91 d general purpose input/output port. sot2 function as a data output pin for uart ch.2. 31 p92 d general purpose input/output port. sck2 function as a clock i/o pin for uart ch.2. 32 p93 d general purpose input/output port. sin3 function as a data input pin for uart ch.3. 33 p94 d general purpose input/output port. sot3 function as a data output pin for uart ch.3. 34 p95 d general purpose input/output port. sck3 function as a clock i/o pin for uart ch.3. 35 p96 c general purpose input/output port . (withstand voltage of 5 v) adtg function as the external trigger input pin when the a/d conv erter is being used. frck function as the external clock input pin when the free-run timer is being used.
mb90330a series ds07-13734-9e 11 (continued) * : for circuit information, refer to ? i/o circuit type?. pin no. pin name i/o circuit type* function 56 to 59 pa0 to pa3 c general purpose input/output port. (withstand voltage of 5 v) in0 to in3 function as the input capt ure ch.0 to ch.3 trigger inputs. 60 to 63 pa4 to pa7 c general purpose input/output port. (withstand voltage of 5 v) out0 to out3 function as the output co mpare ch.0 to ch.3 event output pins. 64 pb0 c general purpose input/output port. (withstand voltage of 5 v) scl1 function as the ch.1 clock i/o pin for the i 2 c interface. set port output to high-z during i 2 c interface operations. 65 pb1 c general purpose input/output port. (withstand voltage of 5 v) sda1 function as the ch.1 data i/o pin for the i 2 c interface. set port output to high-z during i 2 c interface operations. 66 pb2 c general purpose input/output port. (withstand voltage of 5 v) scl2 function as the ch.2 clock i/o pin for the i 2 c interface. set port output to high-z during i 2 c interface operations. 67 pb3 c general purpose input/output port. (withstand voltage of 5 v) sda2 function as the ch.2 data i/o pin for the i 2 c interface. set port output to high-z during i 2 c interface operations. 68 pb4 c general purpose input/output port. (withstand voltage of 5 v) 69, 70 pb5, pb6 d general purpose input/output port. ppg4, ppg5 function as ch.4 and ch.5 output pins for the 8-bit ppg timer. 71 utest c usb test pin. connect this to a pull-down resistor during normal usage. 73 dvm k usb function d ? pin. 74 dvp k usb function d + pin. 77 hvm k usb host d ? pin. 78 hvp k usb host d + pin. 80 hcon e external pull-up resistor connect pin. 36 avcc ? a/d converter power supply pin. 37 avrh j a/d converter external reference power supply pin. 38 avss ? a/d converter power supply pin. 87 to 89 md2 to md0 b operation mode select input pin. 15, 75, 79, 105 vcc ? power supply pin. 16, 47, 72, 76, 106 vss ? power supply pin (gnd).
mb90330a series 12 ds07-13734-9e i/o circuit type (continued) type circuit remarks a ? high-rate oscillation feedback resistor, approx.1 m ? low-rate oscillation feedback resistor, approx.10 m ? with standby control b cmos hysteresis input c ? cmos hysteresis input ? n-ch open drain output d ? cmos output ? cmos hysteresis input (with input interception function at standby) notes : ? share one output buffer because both output of i/o port and internal resource are used. ? share one input buffer because both input of i/o port and internal resource are used. ecmos output f cmos hysteresis input with pull-up resistor x1 x1a x0 x0a clock input standby control signal cmos hysteresis input nout n-ch cmos hysteresis input standby control signal pout nout p-ch n-ch cmos hysteresis input standby control signal pout nout p-ch n-ch r cmos hysteresis input
mb90330a series ds07-13734-9e 13 (continued) type circuit remarks g ? cmos output ? cmos hysteresis input (with input interception function at standby) with open drain control signal h ? cmos output ? cmos input (with input interception function at standby) ? with input pull-up register control i ? cmos output ? cmos hysteresis input (with input interception function at standby) ? analog input (the a/d converter analog input is enabled when the corresponding bit in the analog input enable register (ader) is 1.) notes: ? because the output of the i/o port and the output of internal resources are used combinedly, one output buffer is shared. ? because the input of the i/o port and the input of in ternal resources are used combinedly, one input buffer is shared. j a/d converter (avrh) voltage input pin pout nout p-ch n-ch open drain control signal standby control signal cmos hysteresis input pout nout p-ch r n-ch ctl cmos input standby control signal pout nout p-ch n-ch cmos hysteresis input standby control signal a/d converter analog input p-ch n-ch p-ch n-ch a/d converter analog input enable signal avrh input
mb90330a series 14 ds07-13734-9e (continued) type circuit remarks k usb i/o pin l ? cmos output ? cmos input ? with standby control d + d ? + + + pout nout p-ch n-ch cmos input standby control signal
mb90330a series ds07-13734-9e 15 handling devices 1. preventing latch-up and turning on power supply latch - up may occur on cmos ic un der the following conditions: ? if a voltage higher than v cc or lower than v ss is applied to input and output pins. ? a voltage higher than the rat ed voltage is applied between v cc pin and v ss pin. ? if the av cc power supply is turned on before the v cc voltage. ensure that you apply a voltage to the analog power supply at the same time as v cc or after you turn on the digital power supply (when you perform power-off, turn of f the analog power supply first or at the same time as v cc and the digital power supply). if latch-up occurs, the supply current increases rapidly, sometimes resulting in thermal breakdown of the device. use meticulous care not to let any voltage exceed the maximum rating. 2. treatment of unused pins leaving unused input pins unconnected ca n cause abnormal operation or latch - up, leading to permanent damage. unused input pins should always be pulled up or down through resistance of at least 2 k . any unused input/ output pins may be set to output mode and left open, or set to input mode and treat ed the same as unused input pins. if there is unused outp ut pin, make it to open. 3. treatment of power supply pins on models with a/d converters even when the a/d converters are not in use, be sure to make the necessary connections av cc = avrh = v cc , and av ss = v ss . 4. about the attention when the external clock is used even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or when recovering from sub clock or stop mode. when suin g an external clock, 25 mhz should be the upper frequency limit. the following figure shows a sample use of external clock signals. 5. treatment of power supply pins (v cc /v ss ) in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission le vel, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current ra ting. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 f between v cc pin and v ss pin near this device. x0 x1 open ? using external clock
mb90330a series 16 ds07-13734-9e 6. about crystal oscillator circuit noise near the x0/x1 pins and x0a/x1a pins may cause the device to malfunction. design the printed circuit board so that x0/x1 pins and x0a/x1a pins, the crys tal oscillator (or the ceramic oscillator) and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended to design the pc board artwork with the x0/x1 pins and x0a/x1a pins surrounded by ground plane because stable operation can be expected with such a layout. please ask the crystal maker to evaluate the oscillatio nal characteristics of the crystal and this device. 7. caution on operations during pll clock mode on this microcontroller, if in case t he crystal oscillator breaks off or an ex ternal reference clock input stops while the pll clock mode is selected, a self-oscillator circuit contained in the pll may c ontinue its operation at its self-running frequency. however, fujitsu will not guarant ee results of operations if such failure occurs. 8. stabilization of supply voltage a sudden change in the supply voltage may cause t he device to malfunction even within the v cc supply voltage operating range. for stabilization reference, t he supply voltage should be stabilized so that v cc ripple variations (peak-to-peak value) at commercial frequencies (50 hz/60 hz) fall below 10 % of the standard v cc supply voltage and the transient regulation does not exceed 0.1 v/ms at temporary changes such as power supply switching. 9. when the dual-supply is used as a single-supply device if you are using only a single-system of the mb90330a seri es that come in the dual-s ystem product, use it with x0a = v ss : x1a = open. 10. writing to flash memory for serial writing to flash memory, always make sure that the operating voltage v cc is between 3.13 v and 3.6 v. for normal writing to flash memory, always make sure that the operating voltage v cc is between 3.0 v and 3.6 v. 11. serial communication there is a possibility to receive wrong data due to noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider receiving of wrong data when designing the sy stem. for example, apply a checksum to detect an error. if an error is detected, retransmit the data.
mb90330a series ds07-13734-9e 17 block diagram f 2 mc-16lx cpu ram 8/16-bit ppg timer ch.0 to ch.5* inp u t capt u re ch.0 to ch.3 16-bit free-r u n timer o u tp u t compare ch.0 to ch.3 16-bit pwc sio dmac 8/10-bit a/d converter external interr u pt i/o port (port 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b) 16-bit reload timer ch.0 to ch.2 usb (f u nction) (host) clock control circ u it interr u pt controller rom uart/sio ch.0 to ch.3 i 2 c ch.0 to ch.2 p00 p07 p10 p17 p20 p27 p30 p37 p40 p47 p50 p57 p60 p67 x0, x1 x0a,x1a rst md0 to md2 sin0 to sin3 sot0 to sot3 sck0 to sck3 scl0 to scl2 sda0 to sda2 int0 to int7 av cc avrh av ss an0 to an15 adtg dvp dvm hvp hvm hcon utest tot0 to tot2 tin0 to tin2 ppg0 to ppg5 frck in0 to in3 out0 to out3 pwc sin sot sck p80 p87 p70 p77 p90 p96 pb0 pb6 pa 0 pa 7 * : channel for use in 8-bit mode. 3 channels (ch.1, ch.3, ch.5) are used in 16-bit mode. note : i/o ports share pins with peripheral function (resources) . for details, refer to ? pin assignment? and ? pin description?. note also that pins used for peripheral func tion (resources) cannot serve as i/o ports. internal data bus
mb90330a series 18 ds07-13734-9e memory map memory map of mb90330a series (1/3) ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 007100 h 007900 h 008000 h f80000 h f8ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h MB90V330A ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 006100 h 007900 h 008000 h f80000 h f8ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h mb90f334a ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 004100 h 007900 h 008000 h f80000 h f8ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h mb90333a rom (ff bank) rom (fe bank) rom (fd bank) rom (fc bank) rom (fb bank) rom (fa bank) rom (f9 bank) rom (f8 bank) rom (ff bank) rom (fe bank) rom (fd bank) rom (fb bank) rom (fa bank) rom (f9 bank) rom (ff bank) rom (fe bank) rom (fd bank) rom (fb bank) rom (image of ff bank) rom (image of ff bank) rom (image of ff bank) peripheral area peripheral area peripheral area peripheral area peripheral area peripheral area ram area (28 kbytes) ram area (24 kbytes) ram area (16 kbytes) register register register ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 007900 h 008000 h f80000 h f8ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h mb90f335a rom (ff bank) rom (fe bank) rom (fd bank) rom (fc bank) rom (fb bank) rom (fa bank) rom (f9 bank) rom (f8 bank) rom (image of ff bank) peripheral area peripheral area ram area (30 kbytes) register single chip mode (with rom mirror function)
mb90330a series ds07-13734-9e 19 memory map of mb90330a series (2/3) ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 007100 h 007900 h 008000 h f80000 h f8ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h MB90V330A ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 006100 h 007900 h 008000 h f80000 h f8ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h mb90f334a ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 004100 h 007900 h 008000 h f80000 h f8ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h mb90333a rom (ff bank) rom (fe bank) rom (fd bank) rom (fc bank) rom (fb bank) rom (fa bank) rom (f9 bank) rom (f8 bank) rom (ff bank) rom (fe bank) rom (fd bank) rom (fb bank) rom (fa bank) rom (f9 bank) rom (ff bank) rom (fe bank) rom (fd bank) rom (fb bank) rom (image of ff bank) rom (image of ff bank) rom (image of ff bank) peripheral area peripheral area peripheral area peripheral area peripheral area peripheral area ram area (28 kbytes) ram area (24 kbytes) ram area (16 kbytes) register register register * 1 * 1 * 2 * 2 external area external area external area external area external area external area external area ffffff h fbffff h 00ffff h 007fff h 000000 h f90000 h 0000fb h 000100 h 007900 h 008000 h f80000 h f8ffff h f9ffff h fa0000 h faffff h fb0000 h fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h mb90f335a rom (ff bank) rom (fe bank) rom (fd bank) rom (fc bank) rom (fb bank) rom (fa bank) rom (f9 bank) rom (f8 bank) rom (image of ff bank) peripheral area peripheral area ram area (30 kbytes) register external area external area internal rom external bus mode (with rom mirror function) *1 : in the area of f80000 h to f8ffff h and fc0000 h to fcffff h at mb90f334a, a value of ?1? is read at read operating. *2 : in the area of fa0000 h to faffff h and fc0000 h to fcffff h at mb90333a, a value of ?1? is read at read operating.
mb90330a series 20 ds07-13734-9e memory map of mb90330a series (3/3) notes: ? when the rom mirror function register has be en set, the mirror image da ta at higher addresses (?ff8000 h to ffffff h ?) of bank ff is visible from the higher addresses (?008000 h to 00ffff h ?) of bank 00. ? the rom mirror function is effectiv e for using the c compiler small model. ? the lower 16-bit addresses of bank ff are equivale nt to those of bank 00. since the rom area in bank ff exceeds 48 kbytes, however, the mirror imag e of all the data in the rom area cannot be reproduced in bank 00. ? when the c compiler small model is used, the data table mirror image can be shown at ?008000 h to 00ffff h ? by storing the data table at ?ff8000 h to ffffff h ?. therefore, data tables in the rom area can be referred without declaring t he far addressing with the pointer. ? mb90f335a has the larger size of ram area than mb 90v330a, so that the emulation memory area needs to be set in the tools for a lar ger size of emulation area than 007100 h . for details of setting, please refer to ?notes on debug environment setting for mb90330a series? by clicking "application note" at the following url. http://edevice.fujitsu.com/micom/en-support/ ? 3 cycles are required to access to the emulation memory area (007100 h to 0078ff h ), which is 1 cycle more than to the mounted ram area. ffffff h 007fff h 000000 h 0000fb h 000100 h 007100 h 007900 h 008000 h MB90V330A ffffff h 007fff h 000000 h 0000fb h 000100 h 006100 h 007900 h 008000 h mb90f334a ffffff h 007fff h 000000 h 0000fb h 000100 h 004100 h 007900 h 008000 h mb90333a peripheral area peripheral area peripheral area peripheral area peripheral area peripheral area ram area (28 kbytes) ram area (24 kbytes) ram area (16 kbytes) register register register external area external area external area external area external area ffffff h 007fff h 000000 h 0000fb h 000100 h 007900 h 008000 h mb90f335a peripheral area peripheral area ram area (30 kbytes) register external area external area external rom external bus mode
mb90330a series ds07-13734-9e 21 f 2 mc - 16lx cpu programming model ? dedicated register ? general purpose register ? processor status ah al dpr pcb dtb usb ssb adb 8-bit 16-bit 32-bit usp ssp ps pc accumulator user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register r1 r0 r3 r2 r5 r4 r7 r6 rw0 rw1 rw2 rw3 16-bit 000180 h + rp 10 h rw4 rw5 rw6 rw7 rl0 rl1 rl2 rl3 msb lsb ilm 15 13 ps rp ccr 12 8 70 bit
mb90330a series 22 ds07-13734-9e i/o map (continued) address register abbreviation register read/ write resource name initial value 000000 h pdr0 port 0 data register r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w port 5 xxxxxxxx b 000006 h pdr6 port 6 data register r/w port 6 xxxxxxxx b 000007 h pdr7 port 7 data register r/w port 7 xxxxxxxx b 000008 h pdr8 port 8 data register r/w port 8 xxxxxxxx b 000009 h pdr9 port 9 data register r/w port 9 - xxxxxxx b 00000a h pdra port a data register r/w port a xxxxxxxx b 00000b h prohibited 00000c h pdrb port b data register r/w port b - xxxxxxx b 00000d h ddrb port b direction register r/w port b - 0 0 0 0 0 0 0 b 00000e h prohibited 00000f h 000010 h ddr0 port 0 direction register r/w port 0 0 0 0 0 0 0 0 0 b 000011 h ddr1 port 1 direction register r/w port 1 0 0 0 0 0 0 0 0 b 000012 h ddr2 port 2 direction register r/w port 2 0 0 0 0 0 0 0 0 b 000013 h ddr3 port 3 direction register r/w port 3 0 0 0 0 0 0 0 0 b 000014 h ddr4 port 4 direction register r/w port 4 0 0 0 0 0 0 0 0 b 000015 h ddr5 port 5 direction register r/w port 5 0 0 0 0 0 0 0 0 b 000016 h ddr6 port 6 direction register r/w port 6 0 0 0 0 0 0 0 0 b 000017 h ddr7 port 7 direction register r/w port 7 0 0 0 0 0 0 0 0 b 000018 h ddr8 port 8 direction register r/w port 8 0 0 0 0 0 0 0 0 b 000019 h ddr9 port 9 direction register r/w port 9 - 0 0 0 0 0 0 0 b 00001a h ddra port a direction register r/w port a 0 0 0 0 0 0 0 0 b 00001b h odr4 port 4 output pin register r/w port 4 (open drain control) 0 0 0 0 0 0 0 0 b 00001c h rdr0 port 0 pull-up resistance register r/w port 0 (pull-up) 0 0 0 0 0 0 0 0 b 00001d h rdr1 port 1 pull-up resistance register r/w port 1 (pull-up) 0 0 0 0 0 0 0 0 b 00001e h ader0 analog input enable register 0 r/w port 7, 8, a/d 1 1 1 1 1 1 1 1 b 00001f h ader1 analog input enable register 1 r/w port 7, 8, a/d 1 1 1 1 1 1 1 1 b 000020 h smr0 serial mode register 0 r/w uart0 0 0 1 0 0 0 0 0 b 000021 h scr0 serial control register 0 r/w 0 0 0 0 0 1 0 0 b 000022 h sidr0 serial input data register 0 r xxxxxxxx b sodr0 serial output data register 0 w 000023 h ssr0 serial status register 0 r/w 0 0 0 0 1 0 0 0 b 000024 h utrlr0 uart prescaler reload register 0 r/w communication prescaler (uart0) 0 0 0 0 0 0 0 0 b 000025 h utcr0 uart prescaler control register 0 r/w 0 0 0 0 - 0 0 0 b
mb90330a series ds07-13734-9e 23 (continued) address register abbreviation register read/ write resource name initial value 000026 h smr1 serial mode register 1 r/w uart1 0 0 1 0 0 0 0 0 b 000027 h scr1 serial control register 1 r/w 0 0 0 0 0 1 0 0 b 000028 h sidr1 serial input data register 1 r xxxxxxxx b sodr1 serial output data register 1 w 000029 h ssr1 serial status register 1 r/w 0 0 0 0 1 0 0 0 b 00002a h utrlr1 uart prescaler reload register 1 r/w communication prescaler (uart1) 0 0 0 0 0 0 0 0 b 00002b h utcr1 uart prescaler control register 1 r/w 0 0 0 0 - 0 0 0 b 00002c h smr2 serial mode register 2 r/w uart2 0 0 1 0 0 0 0 0 b 00002d h scr2 serial control register 2 r/w 0 0 0 0 0 1 0 0 b 00002e h sidr2 serial input data register 2 r xxxxxxxx b sodr2 serial output data register 2 w 00002f h ssr2 serial status register 2 r/w 0 0 0 0 1 0 0 0 b 000030 h utrlr2 uart prescaler reload register 2 r/w communication prescaler (uart2) 0 0 0 0 0 0 0 0 b 000031 h utcr2 uart prescaler control register 2 r/w 0 0 0 0 - 0 0 0 b 000032 h smr3 serial mode register 3 r/w uart3 0 0 1 0 0 0 0 0 b 000033 h scr3 serial control register 3 r/w 0 0 0 0 0 1 0 0 b 000034 h sidr3 serial input data register 3 r xxxxxxxx b sodr3 serial output data register 3 w 000035 h ssr3 serial status register 3 r/w 0 0 0 0 1 0 0 0 b 000036 h utrlr3 uart prescaler reload register 3 r/w communication prescaler (uart3) 0 0 0 0 0 0 0 0 b 000037 h utcr3 uart prescaler control register 3 r/w 0 0 0 0 - 0 0 0 b 000038 h to 00003b h prohibited 00003c h enir dtp/interrupt enable register r/w dtp/external interrupt 0 0 0 0 0 0 0 0 b 00003d h eirr dtp/interrupt source register r/w 0 0 0 0 0 0 0 0 b 00003e h elvr request level setting register lower r/w 0 0 0 0 0 0 0 0 b 00003f h request level setting register upper r/w 0 0 0 0 0 0 0 0 b 000040 h adcs0 a/d control status register lower r/w 8/10-bit a/d converter 0 0 - - - - - 0 b 000041 h adcs1 a/d control status regi ster upper r/w 0 0 0 0 0 0 0 0 b 000042 h adcr0 a/d data register lower r/w xxxxxxxx b 000043 h adcr1 a/d data register upper r/w 0 0 1 0 1 xxx b 000044 h prohibited 000045 h admr a/d conversion channel selection register r/w 8/10-bit a/d converter 0 0 0 0 0 0 0 0 b 000046 h ppgc0 ppg0 operation mode control register r/w ppg ch.0 0x0 0 0xx1 b 000047 h ppgc1 ppg1 operation mode control register r/w ppg ch.1 0x0 0 0 0 0 1 b 000048 h ppgc2 ppg2 operation mode control register r/w ppg ch.2 0x0 0 0xx1 b
mb90330a series 24 ds07-13734-9e (continued) address register abbreviation register read/ write resource name initial value 000049 h ppgc3 ppg3 operation mode control re gister r/w ppg ch.3 0x0 0 0 0 0 1 b 00004a h ppgc4 ppg4 operation mode control register r/w ppg ch.4 0x0 0 0xx1 b 00004b h ppgc5 ppg5 operation mode control re gister r/w ppg ch.5 0x0 0 0 0 0 1 b 00004c h ppg01 ppg0 and ppg1 output control register r/w ppg ch.0/ch.1 0 0 0 0 0 0xx b 00004d h prohibited 00004e h ppg23 ppg2 and ppg3 output control register r/w ppg ch.2/ch.3 0 0 0 0 0 0 xx b 00004f h prohibited 000050 h ppg45 ppg4 and ppg5 output control register r/w ppg ch.4/ch.5 0 0 0 0 0 0 xx b 000051 h prohibited 000052 h ics01 input capture control status register 01 r/w input capture ch.0/ch.1 0 0 0 0 0 0 0 0 b 000053 h ics23 input capture control status register 23 r/w input capture ch.2/ch.3 0 0 0 0 0 0 0 0 b 000054 h ocs0 output compare control register ch.0 lower r/w output compare ch.0/ch.1 0 0 0 0 - - 0 0 b 000055 h ocs1 output compare control register ch.1 upper r/w - - - 0 0 0 0 0 b 000056 h ocs2 output compare control register ch.2 lower r/w output compare ch.2/ch.3 0 0 0 0 - - 0 0 b 000057 h ocs3 output compare control register ch.3 upper r/w - - - 0 0 0 0 0 b 000058 h smcs serial mode control status register r/w extended serial i/o xxxx0 0 0 0 b 000059 h 0 0 0 0 0 0 1 0 b 00005a h sdr serial data register r/w xxxxxxxx b 00005b h sdcr communication prescaler control register r/w communication prescaler 0xxx0 0 0 0 b 00005c h pwcsr pwc control status register r/w 16-bit pwc timer 0 0 0 0 0 0 0 0 b 00005d h 0 0 0 0 0 0 0 x b 00005e h pwcr pwc data buffer register r/w 0 0 0 0 0 0 0 0 b 00005f h 0 0 0 0 0 0 0 0 b 000060 h divr pwc dividing ratio control register r/w - - - - - - 0 0 b 000061 h prohibited 000062 h tmcsr0 timer control status register 0 r/w 16-bit reload timer ch.0 0 0 0 0 0 0 0 0 b 000063 h xxxx 0 0 0 0 b 000064 h tmr0 16-bit timer register 0 lower r xxxxxxxx b tmrlr0 16-bit reload register 0 lower w xxxxxxxx b 000065 h tmr0 16-bit timer register 0 upper r xxxxxxxx b tmrlr0 16-bit reload register 0 upper w xxxxxxxx b
mb90330a series ds07-13734-9e 25 (continued) address register abbreviation register read/ write resource name initial value 000066 h tmcsr1 timer control status register 1 r/w 16-bit reload timer ch.1 0 0 0 0 0 0 0 0 b 000067 h xxxx 0 0 0 0 b 000068 h tmr1 16-bit timer register 1 lower r xxxxxxxx b tmrlr1 16-bit reload register 1 lower w xxxxxxxx b 000069 h tmr1 16-bit timer register 1 upper r xxxxxxxx b tmrlr1 16-bit reload register 1 upper w xxxxxxxx b 00006a h tmcsr2 timer control status register 2 r/w 16-bit reload timer ch.2 0 0 0 0 0 0 0 0 b 00006b h xxxx 0 0 0 0 b 00006c h tmr2 16-bit timer register 2 lower r xxxxxxxx b tmrlr2 16-bit reload register 2 lower w xxxxxxxx b 00006d h tmr2 16-bit timer register 2 upper r xxxxxxxx b tmrlr2 16-bit reload register 2 upper w xxxxxxxx b 00006e h prohibited 00006f h romm rom mirror function selection register w rom mirror function selection module - - - - - - 1 1 b 000070 h ibsr0 i 2 c bus status register 0 r i 2 c bus interface ch.0 0 0 0 0 0 0 0 0 b 000071 h ibcr0 i 2 c bus control register 0 r/w 0 0 0 0 0 0 0 0 b 000072 h iccr0 i 2 c bus clock control register 0 r/w xx 0 xxxxx b 000073 h iadr0 i 2 c bus address register 0 r/w xxxxxxxx b 000074 h idar0 i 2 c bus data register 0 r/w xxxxxxxx b 000075 h prohibited 000076 h ibsr1 i 2 c bus status register 1 r i 2 c bus interface ch.1 0 0 0 0 0 0 0 0 b 000077 h ibcr1 i 2 c bus control register 1 r/w 0 0 0 0 0 0 0 0 b 000078 h iccr1 i 2 c bus clock control register 1 r/w xx 0 xxxxx b 000079 h iadr1 i 2 c bus address register 1 r/w xxxxxxxx b 00007a h idar1 i 2 c bus data register 1 r/w xxxxxxxx b 00007b h prohibited 00007c h ibsr2 i 2 c bus status register 2 r i 2 c bus interface ch.2 0 0 0 0 0 0 0 0 b 00007d h ibcr2 i 2 c bus control register 2 r/w 0 0 0 0 0 0 0 0 b 00007e h iccr2 i 2 c bus clock control register 2 r/w xx 0 xxxxx b 00007f h iadr2 i 2 c bus address register 2 r/w xxxxxxxx b 000080 h idar2 i 2 c bus data register 2 r/w xxxxxxxx b 000081 h to 000085 h prohibited
mb90330a series 26 ds07-13734-9e (continued) address register abbreviation register read/ write resource name initial value 000086 h tcdt timer data register lower r/w 16-bit free-run timer 0 0 0 0 0 0 0 0 b 000087 h timer data register upper r/w 0 0 0 0 0 0 0 0 b 000088 h tccs timer control status regist er lower r/w 0 0 0 0 0 0 0 0 b 000089 h timer control status regist er upper r/w 0 - - 0 0 0 0 0 b 00008a h cpclr compare clear register lower r/w xxxxxxxx b 00008b h compare clear register upper r/w xxxxxxxx b 00008c h to 00009a h prohibited 00009b h dcsr dma descriptor channel specification register r/w dmac 0 0 0 0 0 0 0 0 b 00009c h dsrl dma status register lower r/w 0 0 0 0 0 0 0 0 b 00009d h dsrh dma status register upper r/w 0 0 0 0 0 0 0 0 b 00009e h pacsr program address detection control status register r/w address match detection 0 0 0 0 0 0 0 0 b 00009f h dirr delay interruption factor generation/ release register r/w delay interrupt - - - - - - - 0 b 0000a0 h lpmcr low power consumption mode control register r/w low power consumption control circuit 0 0 0 1 1 0 0 0 b 0000a1 h ckscr clock selection register r/w clock 1 1 1 1 1 1 0 0 b 0000a2 h prohibited 0000a3 h 0000a4 h dssr dma stop status register r/w dmac 0 0 0 0 0 0 0 0 b 0000a5 h arsr automatic ready function selection register w external pin 0 0 1 1- - 0 0 b 0000a6 h hacr external address output control register w ? ? ? ? ? ? ? ? b 0000a7 h epcr bus control signal selection register w 1 0 0 0 ? 1 0 - b 0000a8 h wdtc watchdog timer control register r/w watchdog timer x - xxx 1 1 1 b 0000a9 h tbtc time-base timer control register r/w time-base timer 1 - - 0 0 1 0 0 b 0000aa h wtc watch timer control register r/w watch timer 1 0 0 0 1 0 0 0 b 0000ab h prohibited 0000ac h derl dma enable register lower r/w dmac 0 0 0 0 0 0 0 0 b 0000ad h derh dma enable register upper r/w 0 0 0 0 0 0 0 0 b 0000ae h fmcs flash memory control status register r/w flash memory i/f 0 0 0 x 0 0 0 0 b 0000af h prohibited
mb90330a series ds07-13734-9e 27 (continued) address register abbreviation register read/ write resource name initial value 0000b0 h icr00 interrupt control register 00 r/w interrupt controller 0 0 0 0 0 1 1 1 b 0000b1 h icr01 interrupt control register 01 r/w 0 0 0 0 0 1 1 1 b 0000b2 h icr02 interrupt control register 02 r/w 0 0 0 0 0 1 1 1 b 0000b3 h icr03 interrupt control register 03 r/w 0 0 0 0 0 1 1 1 b 0000b4 h icr04 interrupt control register 04 r/w 0 0 0 0 0 1 1 1 b 0000b5 h icr05 interrupt control register 05 r/w 0 0 0 0 0 1 1 1 b 0000b6 h icr06 interrupt control register 06 r/w 0 0 0 0 0 1 1 1 b 0000b7 h icr07 interrupt control register 07 r/w 0 0 0 0 0 1 1 1 b 0000b8 h icr08 interrupt control register 08 r/w 0 0 0 0 0 1 1 1 b 0000b9 h icr09 interrupt control register 09 r/w 0 0 0 0 0 1 1 1 b 0000ba h icr10 interrupt control register 10 r/w 0 0 0 0 0 1 1 1 b 0000bb h icr11 interrupt control register 11 r/w 0 0 0 0 0 1 1 1 b 0000bc h icr12 interrupt control register 12 r/w 0 0 0 0 0 1 1 1 b 0000bd h icr13 interrupt control register 13 r/w 0 0 0 0 0 1 1 1 b 0000be h icr14 interrupt control register 14 r/w 0 0 0 0 0 1 1 1 b 0000bf h icr15 interrupt control register 15 r/w 0 0 0 0 0 1 1 1 b 0000c0 h hcnt0 host control register 0 r/w usb host 0 0 0 0 0 0 0 0 b 0000c1 h hcnt1 host control register 1 r/w 0 0 0 0 0 0 0 1 b 0000c2 h hirq host interruption register r/w 0 0 0 0 0 0 0 0 b 0000c3 h herr host error status register r/w 0 0 0 0 0 0 1 1 b 0000c4 h hstate host state status register r/w xx 0 1 0 0 1 0 b 0000c5 h hfcomp sof interrupt frame compare reg- ister r/w 0 0 0 0 0 0 0 0 b 0000c6 h hrtimer retry timer setting register r/w 0 0 0 0 0 0 0 0 b 0000c7 h r/w 0 0 0 0 0 0 0 0 b 0000c8 h r/w xxxxxx 0 0 b 0000c9 h hadr host address register r/w x 0 0 0 0 0 0 0 b 0000ca h heof eof setting register r/w 0 0 0 0 0 0 0 0 b 0000cb h r/w xx 0 0 0 0 0 0 b 0000cc h hframe frame setting register r/w 0 0 0 0 0 0 0 0 b 0000cd h r/w xxxxx 0 0 0 b 0000ce h htoken host token end point register r/w 0 0 0 0 0 0 0 0 b 0000cf h prohibited 0000d0 h udcc udc control register r/w usb function 1 0 1 0 0 0 0 0 b 0000d1 h r/w 0 0 0 0 0 0 0 0 b
mb90330a series 28 ds07-13734-9e (continued) address register abbreviation register read/ write resource name initial value 0000d2 h ep0c ep0 control register r/w usb function 0 1 0 0 0 0 0 0 b 0000d3 h r/w xxxx 0 0 0 0 b 0000d4 h ep1c ep1 control register r/w 0 0 0 0 0 0 0 0 b 0000d5 h r/w 0 1 1 0 0 0 0 1 b 0000d6 h ep2c ep2 control register r/w 0 1 0 0 0 0 0 0 b 0000d7 h r/w 0 1 1 0 0 0 0 0 b 0000d8 h ep3c ep3 control register r/w 0 1 0 0 0 0 0 0 b 0000d9 h r/w 0 1 1 0 0 0 0 0 b 0000da h ep4c ep4 control register r/w 0 1 0 0 0 0 0 0 b 0000db h r/w 0 1 1 0 0 0 0 0 b 0000dc h ep5c ep5 control register r/w 0 1 0 0 0 0 0 0 b 0000dd h r/w 0 1 1 0 0 0 0 0 b 0000de h tmsp time stamp register r 0 0 0 0 0 0 0 0 b 0000df h r xxxxx0 0 0 b 0000e0 h udcs udc status register r/w xx0 0 0 0 0 0 b 0000e1 h udcie udc interrupt enable register r/w, r 0 0 0 0 0 0 0 0 b 0000e2 h ep0is ep0i status register r/w xxxxxxxx b 0000e3 h r/w 1 0 xxx 1 xx b 0000e4 h ep0os ep0o status register r/w, r 0 xxxxxxx b 0000e5 h r/w 1 0 0 xx 0 0 0 b 0000e6 h ep1s ep1 status register r xxxxxxxx b 0000e7 h r/w, r 1 0 0 0 0 0 0 x b 0000e8 h ep2s ep2 status register r xxxxxxxx b 0000e9 h r/w, r 1 0 0 0 0 0 0 0 b 0000ea h ep3s ep3 status register r xxxxxxxx b 0000eb h r/w, r 1 0 0 0 0 0 0 0 b 0000ec h ep4s ep4 status register r xxxxxxxx b 0000ed h r/w, r 1 0 0 0 0 0 0 0 b 0000ee h ep5s ep5 status register r xxxxxxxx b 0000ef h r/w, r 1 0 0 0 0 0 0 0 b 0000f0 h ep0dt ep0 data register r/w xxxxxxxx b 0000f1 h r/w xxxxxxxx b 0000f2 h ep1dt ep1 data register r/w xxxxxxxx b 0000f3 h r/w xxxxxxxx b 0000f4 h ep2dt ep2 data register r/w xxxxxxxx b 0000f5 h r/w xxxxxxxx b 0000f6 h ep3dt ep3 data register r/w xxxxxxxx b 0000f7 h r/w xxxxxxxx b
mb90330a series ds07-13734-9e 29 (continued) address register abbreviation register read/ write resource name initial value 0000f8 h ep4dt ep4 data register r/w usb function xxxxxxxx b 0000f9 h r/w xxxxxxxx b 0000fa h ep5dt ep5 data register r/w xxxxxxxx b 0000fb h r/w xxxxxxxx b 0000fc h to 0000ff h prohibited 000100 h to # h ram area 001ff0 h padr0 program address detection register ch.0 lower r/w address match detection xxxxxxxx b 001ff1 h program address detection register ch.0 middle r/w xxxxxxxx b 001ff2 h program address detection register ch.0 upper r/w xxxxxxxx b 001ff3 h padr1 program address detection register ch.1 lower r/w xxxxxxxx b 001ff4 h program address detection register ch.1 middle r/w xxxxxxxx b 001ff5 h program address detection register ch.1 upper r/w xxxxxxxx b # h to 0078ff h unused area 007900 h prll0 ppg reload register lower ch.0 r/w ppg ch.0 xxxxxxxx b 007901 h prlh0 ppg reload register upper ch.0 r/w xxxxxxxx b 007902 h prll1 ppg reload register lower ch.1 r/w ppg ch.1 xxxxxxxx b 007903 h prlh1 ppg reload register upper ch.1 r/w xxxxxxxx b 007904 h prll2 ppg reload register lower ch.2 r/w ppg ch.2 xxxxxxxx b 007905 h prlh2 ppg reload register upper ch.2 r/w xxxxxxxx b 007906 h prll3 ppg reload register lower ch.3 r/w ppg ch.3 xxxxxxxx b 007907 h prlh3 ppg reload register upper ch.3 r/w xxxxxxxx b 007908 h prll4 ppg reload register lower ch.4 r/w ppg ch.4 xxxxxxxx b 007909 h prlh4 ppg reload register upper ch.4 r/w xxxxxxxx b 00790a h prll5 ppg reload register lower ch.5 r/w ppg ch.5 xxxxxxxx b 00790b h prlh5 ppg reload register upper ch.5 r/w xxxxxxxx b 00790c h to 00790f h prohibited
mb90330a series 30 ds07-13734-9e (continued) ? explanation on read/write ? explanation on initial values note : no i/o instruction can be used for registers located between 007900 h and 007fff h . address register abbreviation register read/ write resource name initial value 007910 h ipcp0 input capture data register lower ch.0 r input capture ch.0/ch.1 xxxxxxxx b 007911 h input capture data register upper ch.0 r xxxxxxxx b 007912 h ipcp1 input capture data register lower ch.1 r xxxxxxxx b 007913 h input capture data register upper ch.1 r xxxxxxxx b 007914 h ipcp2 input capture data register lower ch.2 r input capture ch.2/ch.3 xxxxxxxx b 007915 h input capture data register upper ch.2 r xxxxxxxx b 007916 h ipcp3 input capture data register lower ch.3 r xxxxxxxx b 007917 h input capture data register upper ch.3 r xxxxxxxx b 007918 h occp0 output compare register lower ch.0 r/w output compare ch.0/ch.1 xxxxxxxx b 007919 h output compare register upper ch.0 r/w xxxxxxxx b 00791a h occp1 output compare register lower ch.1 r/w xxxxxxxx b 00791b h output compare register upper ch.1 r/w xxxxxxxx b 00791c h occp2 output compare register lower ch.2 r/w output compare ch.2/ch.3 xxxxxxxx b 00791d h output compare register upper ch.2 r/w xxxxxxxx b 00791e h occp3 output compare register lower ch.3 r/w xxxxxxxx b 00791f h output compare register upper ch.3 r/w xxxxxxxx b 007920 h dbapl dma buffer address pointer lower 8-bit r/w dmac xxxxxxxx b 007921 h dbapm dma buffer address pointer middle 8-bit r/w xxxxxxxx b 007922 h dbaph dma buffer address pointer upper 8-bit r/w xxxxxxxx b 007923 h dmacs dma control register r/w xxxxxxxx b 007924 h dioal dma i/o register address pointer lower 8-bit r/w xxxxxxxx b 007925 h dioah dma i/o register address pointer upper 8-bit r/w xxxxxxxx b 007926 h ddctl dma data counter lower 8-bit r/w xxxxxxxx b 007927 h ddcth dma data counter upper 8-bit r/w xxxxxxxx b 007928 h to 007fff h prohibited r/w : readable / writable r : read only w : write only 0 : initial value is ?0?. 1 : initial value is ?1?. x : initial value is undefined. - : initial value is undefined (none) . ? : initial value of this bit is ?1? or ?0?.
mb90330a series ds07-13734-9e 31 interrupt sources, interrupt vectors, and interrupt control registers (continued) interrupt source ei 2 os support dmac interrupt vector interrupt control register priority number* 1 address icr address reset #08 08 h ffffdc h ?? high int 9 instruction #09 09 h ffffd8 h ?? exceptional treatment #10 0a h ffffd4 h ?? usb function1 0, 1 #11 0b h ffffd0 h icr00 0000b0 h usb function2 2 to 6* 2 #12 0c h ffffcc h usb function3 #13 0d h ffffc8 h icr01 0000b1 h usb function4 #14 0e h ffffc4 h usb host1 #15 0f h ffffc0 h icr02 0000b2 h usb host2 #16 10 h ffffbc h i 2 c ch.0 #17 11 h ffffb8 h icr03 0000b3 h dtp/external interrupt ch.0/ch.1 #18 12 h ffffb4 h i 2 c ch.1 #19 13 h ffffb0 h icr04 0000b4 h dtp/external interrupt ch.2/ch.3 #20 14 h ffffac h i 2 c ch.2 #21 15 h ffffa8 h icr05 0000b5 h dtp/external interrupt ch.4/ch.5 #22 16 h ffffa4 h pwc/reload timer ch.0 14 #23 17 h ffffa0 h icr06 0000b6 h dtp/external interrupt ch.6/ch.7 #24 18 h ffff9c h input capture ch.0/ch.1 7 #25 19 h ffff98 h icr07 0000b7 h reload timer ch.1 #26 1a h ffff94 h input capture ch.2/ch.3 8 #27 1b h ffff90 h icr08 0000b8 h reload timer ch.2 #28 1c h ffff8c h output compare ch.0/ch.1 #29 1d h ffff88 h icr09 0000b9 h ppg ch.0/ch.1 #30 1e h ffff84 h output compare ch.2/ch.3 #31 1f h ffff80 h icr10 0000ba h ppg ch.2/ch.3 #32 20 h ffff7c h uart (send completed) ch.2/ch.3 11 #33 21 h ffff78 h icr11 0000bb h ppg ch.4/ch.5 #34 22 h ffff74 h uart (reception completed) ch.2/ch.3 10 #35 23 h ffff70 h icr12 0000bc h a/d converter/free-run timer 15 #36 24 h ffff6c h uart (send completed) ch.0/ch.1 13 #37 25 h ffff68 h icr13 0000bd h extended serial i/o 9 #38 26 h ffff64 h uart (reception completed) ch.0/ch.1 12 #39 27 h ffff60 h icr14 0000be h time-base timer/watch timer #40 28 h ffff5c h flash memory status #41 29 h ffff58 h icr15 0000bf h delay interrupt output module #42 2a h ffff54 h low
mb90330a series 32 ds07-13734-9e (continued) : available, ei 2 os stop function provided (the interrupt reques t flag is cleared by the interrupt clear signal. with a stop request). : available (the interrupt request flag is cleared by the interrupt clear signal.) : available when any interrupt source sharing icr is not used. : unavailable *1 : if the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has priority. *2 : ch.2 and 3 can also be us ed during usb host operation. notes : ? if the same interrupt control register (icr) has two interrupt factor s and the use of the ei 2 os is permitted, the ei 2 os is activated when either of the factors is de tected. as any interrupt other than the activation factor is masked while the ei 2 os is running, it is recommended that you should mask either of the interrupt requests when using the ei 2 os. ? the interrupt flag is cleared by the ei 2 os interrupt clear signal for the resource that has two interrupt factors in the same interrupt control register (icr). ? if a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the dmac interrupt clear signal. therefore, when y ou use either of two interrupt factors for the dmac function, another interrupt function is disabled. set the interrupt request permission bit to ?0? in the appropriate resource, and take measures by software polling. ? content of usb interruption factor * : endpoints 1 and 2 can also be used during usb host operation. usb interrupt factor details usb function 1 end point0-in end point0-out usb function 2 end point1-5 * usb function 3 susp sof brst wkup conf usb function 4 spk usb host1 dirq cnnirq urirq rwkirq usb host2 sofirq cmpirq
mb90330a series ds07-13734-9e 33 usb 1. usb function the usb function is an interface supporting the usb (universal serial bus) communications protocol. ? feature of usb function ? correspond to usb full speed ? full speed (12 mbps) is supported. ? the device status is auto-answer. ? bit stripping, bit stuffing, and automa tic generation and check of crc5 and crc16 ? toggle check by data synchronization bit ? automatic response to all standard commands except get/setdescriptor and synchframe commands (these 3 commands can be processed the same way as the class vendor commands). ? the class vendor commands can be rece ived as data and responded via firmware. ? supports up to 6 endpoints (endpoint0 is fixed to control transfer) ? 2 transfer data buffers integrated for each end point (one in buffer and one out buffer for endpoint 0) ? supports automatic transfer mode for transfer da ta via dma (except buffers for endpoint 0)
mb90330a series 34 ds07-13734-9e 2. usb host usb host provides the minimal host operations required and is a function that enables data to be transferred to and from a device without pc intervention. ? feature of usb host ? automatic detection of low speed/full speed transfer ? low speed/full speed transfer support ? automatic detection of co nnection and cutting device ? reset sending function support to usb-bus ? support of in/out/setup/sof token ? in-token handshake packet automatic transmission (excluding stall) ? out-token handshake packet automatic detection ? supports a maximum packet length of 256 bytes. ? error (crc error/toggle error/time-out) various supports ? wake-up function support ? restrictions of usb host * : it corresponds to full speed only, and the hub supports up to one step. : supported : not supported usb host hub support * transfer bulk transfer control transfer interrupt transfer isochronous transfer transfer speed low speed full speed pre packet support sof packet support error crc error toggle error time-out maximum packet < receive data detection of connection and cutting of device transfer speed detection
mb90330a series ds07-13734-9e 35 sector configuration of flash memory ? sector configuration of 3mbit flash memory sa0 (64 kbytes) prohibited prohibited sa1 (64 kbytes) f80000 h f8ffff h f90000 h f9ffff h fa0000 h faffff h fb0000 h fbffff h 00000 h 0ffff h 10000 h 1ffff h 20000 h 2ffff h 30000 h 3ffff h sa2 (64 kbytes) fc0000 h fcffff h fd0000 h fdffff h fe0000 h feffff h ff0000 h ff7fff h 40000 h 4ffff h 50000 h 5ffff h 60000 h 6ffff h 70000 h 77fff h sa3 (64 kbytes) sa4 (64 kbytes) sa5 (32 kbytes) sa6 (8 kbytes) sa7 (8 kbytes) sa8 (16 kbytes) ff8000 h ff9fff h ffa000 h ffbfff h ffc000 h ffffff h 78000 h 79fff h 7a000 h 7bfff h 7c000 h 7ffff h flash memory cpu address writer address * * : the writer address is relative to the cpu address when data is programmed into flash memory by a parallel programmer. programming and erasing by the general-purpose parallel programmer are executed based on writer addresses. 3 mbits flash memory is located in f9 h to ff h bank on the cpu memory map.
mb90330a series 36 ds07-13734-9e ? sector configuration of 4mbit flash memory f80000 h f8ffff h f90000 h f9ffff h fa0000 h faffff h fb0000 h fb7fff h 00000 h 0ffff h 10000 h 1ffff h 20000 h 2ffff h 30000 h 37fff h fb8000 h fb9fff h fba000 h fbbfff h fbc000 h fbffff h fc0000 fcffff 38000 h 39fff h 3a000 h 3bfff h 3c000 h 3ffff h 40000 h 4ffff h fd0000 fdffff fe0000 h feffff h ff0000 h ff7fff h 50000 h 5ffff h 60000 h 6ffff h 70000 h 77fff h 78000 h 79fff h 7a000 h 7bfff h 7c000 h 7ffff h ff8000 h ff9fff h ffa000 h ffbfff h ffc000 h ffffff h sa0 (64 kbytes) sa1 (64 kbytes) sa2 (64 kbytes) sa3 (32 kbytes) sa4 (8 kbytes) sa5 (8 kbytes) sa6 (16 kbytes) sa7 (64 kbytes) sa8 (64 kbytes) sa9 (64 kbytes) sa10 (32 kbytes) sa11 (8 kbytes) sa12 (8 kbytes) sa13 (16 kbytes) flash memory cpu address writer address * * : the writer address is relative to the cpu addr ess when data is programmed into flash memory by a parallel programmer. programming and erasing by the general-purpose parallel programmer are executed based on writer addresses. 4 mbits flash memory is located in f8 h to ff h bank on the cpu memory map.
mb90330a series ds07-13734-9e 37 electrical characteristics 1. absolute maximum ratings *1 : the parameter is based on v ss = av ss = 0.0 v. *2 : be careful not to let av cc exceed v cc , for example, when the power is turned on. *3 : be careful not to let avrh exceed avcc. *4 : v i and v o must not exceed vcc + 0.3 v. however, if the ma ximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *5 : applicable to pins : p60 to p 67, p96, pa0 to pa7, pb0 to pb4, utest (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 4.0 v av cc v ss ? 0.3 v ss + 4.0 v v cc av cc * 2 avrh v ss ? 0.3 v ss + 4.0 v av cc avr 0 v* 3 input voltage* 1 v i v ss ? 0.3 v ss + 4.0 v *4 v ss ? 0.3 v ss + 6.0 v n-ch open-drain (withstand voltage of 5 v i/o)* 5 ? 0.5 v ss + 4.5 v usb i/o output voltage* 1 v o v ss ? 0.3 v ss + 4.0 v *4 ? 0.5 v ss + 4.5 v usb i/o maximum clamp current i clamp ? 2.0 + 2.0 ma *6 total maximum clamp current ? i clamp ?? 20 ma *6 ?l? level maximum output current i ol1 ? 10 ma other than usb i/o* 7 i ol2 ? 43 ma usb i/o* 7 ?l? level average output current i olav1 ? 4ma*8 i olav2 ? 15/4.5 ma usb-io (full speed/ low speed) * 8 ?l? level maximum total output current i ol ? 100 ma ?l? level average total output current i olav ? 50 ma *9 ?h? level maximum output current i oh1 ?? 10 ma other than usb i/o* 7 i oh2 ?? 43 ma usb i/o* 7 ?h? level average output current i ohav1 ?? 4ma*8 i ohav2 ?? 15/ ? 4.5 ma usb-io (full speed/ low speed) * 8 ?h? level maximum total output current i oh ?? 100 ma ?h? level average total output current i ohav ?? 50 ma *9 power consumption pd ? 340 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c ? 55 + 125 c usb i/o
mb90330a series 38 ds07-13734-9e (continued) *6 : ? applicable to pins: p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p70 to p77, p80 to p87, p90 to p95, pb5, pb6 ? use within recommended operating conditions. ? use at dc voltage (current) ? the + b signal should always be applied a limit ing resistance placed between the + b signal and the microcontroller. ? the value of the limiting resist ance should be set so that when the + b signal is applied the input current to the microcontroller pin does not ex ceed rated values, either instant aneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a + b signal is input when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be suff icient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? note that analog system input/outp ut pins other than p60 to p67, p96, pa0 to pa7, pb0 to pb4, dvp, dvm, hvp, hvm, utest, hcon ? sample recommended circuits: *7 : a peak value of an applicable one pi n is specified as a maximum output current. *8 : the average output current specifies the mean value of the current flowing in the relevant single pin during a period of 100 ms. *9 : the average total output current specifies the mean value of the currents flowing in all of the relevant pins during a period of 100 ms. warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb90330a series ds07-13734-9e 39 2. recommended operating conditions (v ss = av ss = 0.0 v) * : applicable to pins : p60 to p67, p96, pa0 to pa7, pb0 to pb4, utest warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outs ide the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 3.0 3.6 v at normal operation (when using usb) 2.7 3.6 v at normal operation (when not using usb) 1.8 3.6 v hold state of stop operation input ?h? voltage v ih 0.7 v cc v cc + 0.3 v cmos input pin v ihs1 0.8 v cc v cc + 0.3 v cmos hysteresis input pin v ihs2 0.8 v cc v ss + 5.3 v n-ch open-drain (withstand voltage of 5 v i/o)* v ihm v cc ? 0.3 v cc + 0.3 v md pin input v ihusb 2.0 v cc + 0.3 v usb pin input input ?l? voltage v il v ss ? 0.3 0.3 v cc v cmos input pin v ils v ss ? 0.3 0.2 v cc v cmos hysteresis input pin v ilm v ss ? 0.3 v ss + 0.3 v md pin input v ilusb v ss 0.8 v usb pin input differential input sensitivity v di 0.2 ? v usb pin input differential common mode input voltage range v cm 0.8 2.5 v usb pin input operating temperature t a ? 40 + 85 c when not using usb 0 + 70 c when using usb, at external bus operation
mb90330a series 40 ds07-13734-9e 3. dc characteristics (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max output ?h? voltage v oh output pins other than p60 to p67, p96, pa0 to pa7, pb0 to pb4, hvp, hvm, dvp, dvm i oh = ? 4.0 ma v cc ? 0.5 ? vcc v hvp, hvm, dvp, dvm r l = 15 k 5 % 2.8 ? 3.6 v output ?l? voltage v ol output pins other than hvp, hvm, dvp, dvm i ol = 4.0 ma vss ? vss + 0.4 v hvp, hvm, dvp, dvm r l = 1.5 k 5 % 0 ? 0.3 v input leak current i il output pins other than p60 to p67, p96, pa0 to pa7, pb0 to pb4, hvp, hvm, dvp, dvm v cc = 3.3 v, vss < v i < v cc ? 10 ?+ 10 a hvp, hvm, dvp, dvm ?? 5 ?+ 5 a pull-up resistance r pull p00 to p07, p10 to p17 v cc = 3.3 v, t a = + 25 c 25 50 100 k open drain output current i liod p60 to p67, p96, pa0 to pa7, pb0 to pb4 ?? 0.1 10 a power supply current i cc v cc v cc = 3.3 v, internal frequency 24 mhz, at normal operating at usb operating (ustp = 0) ? 75 85 ma mb90f334a mb90f335a ? 65 75 ma mb90333a v cc = 3.3 v, internal frequency 24 mhz, at normal operating at non-operating usb (ustp = 1) ? 70 80 ma mb90f334a mb90f335a ? 60 70 ma mb90333a i ccs v cc = 3.3 v, internal frequency 24 mhz, at sleep mode ? 27 40 ma i cts v cc = 3.3 v, internal frequency 24 mhz, at timer mode ? 3.5 10 ma v cc = 3.3 v, internal frequency 3 mhz, at timer mode ? 12ma i ccl v cc = 3.3 v, internal frequency 8 khz, at sub clock operation, (t a = + 25 c) ? 25 150 a
mb90330a series ds07-13734-9e 41 (continued) (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : p60 to p67, p96, pa0 to pa7, and pb0 to pb4 are n-ch open-drain pins usually used as cmos. parameter sym- bol pin name conditions value unit remarks min typ max power supply current i ccls v cc v cc = 3.3 v, internal frequency 8 khz, at sub clock, at sleep operating, (t a = + 25 c) ? 10 50 a i cct v cc = 3.3 v, internal frequency 8 khz, watch mode, (t a = + 25 c) ? 1.5 40 a i cch t a = + 25 c, at stop ? 140 a input capacitance c in other than avcc, avss, vcc, vss ?? 515pf pull-up resistor r up rst ? 25 50 100 k usb i/o output impedance z usb dvp, dvm hvp, hvm ? 3 ? 14
mb90330a series 42 ds07-13734-9e 4. ac characteristics (1)clock input timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol pin name value unit remarks min typ max clock frequency f ch x0, x1 ? 6 ? mhz when oscillator is used 6 ? 24 mhz external clock input f cl x0a, x1a ? 32.768 ? khz clock cycle time t hcyl x0, x1 ? 166.7 ? ns when oscillator is used 166.7 ? 41.7 ns external clock input t lcyl x0a, x1a ? 30.5 ? s input clock pulse width p wh p wl x0 10 ?? ns a reference duty ratio is 30 % to 70 % . p whl p wll x0a ? 15.2 ? s input clock rise time and fall time tcr tcf x0 ?? 5 ns at external clock internal operating clock frequency f cp ? 3 ? 24 mhz when main clock is used f cpl ?? 8.192 ? khz when sub clock is used internal operating clock cycle time t cp ? 42 ? 333 ns when main clock is used t cpl ?? 122.1 ? s when sub clock is used 0.8 v cc 0.2 v cc t cf t cr t hcyl p wh p wl x0 ? clock timing 0.8 v cc 0.2 v cc t cf t cr t lcyl p whl p wll x0a
mb90330a series ds07-13734-9e 43 3 .6 3 .0 2.7 3 61224 ? pll operation guarantee range pll operation guarantee range normal operation assurance range note : when the usb is used, operation is guar anteed at voltages be tween 3.0 v and 3.6 v. relation between power supply voltage and internal operat ion clock frequency internal clock f cp (mhz) power voltage v cc (v) 24 12 6 3 6 24 relation between internal operation cloc k frequency and external clock frequency multiplied by 4 multiplied by 2 multiplied by 1 external clock fc (mhz) external clock internal clock f cp (mhz)
mb90330a series 44 ds07-13734-9e the ac standards assume the followi ng measurement reference voltages. 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc ? input signal waveform hysteresis input pin hysteresis input/other than md input pin ? output signal waveform output pin
mb90330a series ds07-13734-9e 45 (2)clock output timing (v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : t cp : refer to ? (1) clock input timing?. parameter symbol pin name conditions value unit remarks min max cycle time t cyc clk ? t cp ? ns clk clk t chcl clk v cc = 3.0 v to 3.6 v t cp / 2 ? 15 t cp / 2 + 15 ns at f cp = 24 mhz t cp / 2 ? 20 t cp / 2 + 20 ns at f cp = 12 mhz t cp / 2 ? 64 t cp / 2 + 64 ns at f cp = 6 mhz clk t cyc 2.4 v 2.4 v 0.8 v t chcl
mb90330a series 46 ds07-13734-9e (3) reset (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : oscillation time of oscillator is the time that the amplitude r eaches 90%. it takes severa l milliseconds to several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a ceramic oscillator, and 0 milliseconds on an external clock. parameter symbol pin name conditions value unit remarks min max reset input time t rstl rst ? 500 ? ns at normal operating, at time base timer mode, at main sleep mode, at pll sleep mode oscillation time of oscillator* + 500 ns ? s at stop mode, at sub clock mode, at sub sleep mode, at watch mode rst rst x0 500 ns t rstl 0.2 v cc 0.2 v cc t rstl 0.2 v cc 0.2 v cc ? during stop mode, sub clock mo de, sub-sleep mode and watch mode internal operation clock internal reset oscillation time of oscillator oscillation stabilization wait time execute instruction 90 % of amplitude ? during normal operation, time-base timer mode, main sleep mode and pll sleep mode
mb90330a series ds07-13734-9e 47 (4) power-on reset (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? v cc must be lower than 0.2 v before the power supply is turned on. ? the above standard is a value for performing a power-on reset. ? in the device, there are internal registers which is initialized only by a power-on reset. when the initialization of these item s is expected, turn on the power supply according to the standards. ? sudden change of power supply voltage may activate the power-on reset function. when changing the power supply vo ltage during operation as illustrated below, voltage fluctuation should be minimized so that the voltage rises as smoothly as possible. when raising the power, do not use pll clock. however, if voltage drop is 1 v/s or le ss, use of pll clock is allowed during operation. parameter symbol pin name conditions value unit remarks min max power supply rising time t r v cc ? 0.05 30 ms power supply shutdown time t off v cc 1 ? ms waiting time until power-on v cc t r 0.2 v 0.2 v 2.7 v t off 0.2 v v cc 1. 8 v v ss ram data hold the rising edge should be 50 mv/ms or less.
mb90330a series 48 ds07-13734-9e (5) uart0, uart1, uart2, uart3 i/o extended serial timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? above rating is the case of clk synchronous mode. ? c l is a load capacitance value on pins for testing. ? t cp : refer to ? (1) clock input timing?. parameter symbol pin name conditions value unit min max serial clock cycle time t scyc sckx internal shift clock mode output pin is : c l = 80 pf + 1ttl 8 t cp ? ns sck sot delay time t slov sckx, sotx ? 80 + 80 ns valid sin sck t ivsh sckx, sinx 100 ? ns sck valid sin hold time t shix sckx, sinx 60 ? ns serial clock h pulse width t shsl sckx, sinx external shift clock mode output pin is : c l = 80 pf + 1ttl 4 t cp ? ns serial clock l pulse width t slsh sckx, sinx 4 t cp ? ns sck sot delay time t slov sckx, sotx ? 150 ns valid sin sck t ivsh sckx, sinx 60 ? ns sck valid sin hold time t shix sckx, sinx 60 ? ns
mb90330a series ds07-13734-9e 49 ? internal shift clock mode ? external shift clock mode sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc
mb90330a series 50 ds07-13734-9e (6) i 2 c timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : f cp is internal operating clock frequency. refer to ? (1) clock input timing?. *2 : r and c are pull-up resistance of scl and sda lines and load capacitance. *3 : the maximum t hddat only has to be met if the device does not stretch the ?l? width (t low ) of the scl signal. *4 : refer to ? ? note of sda, scl set-up time?. parameter symbol conditions value unit min max scl clock frequency f scl power-supply voltage of external pull-up resistor at 5.0 v. r = 1.2 k , c = 50 pf* 2 power-supply voltage of external pull-up resistor at 3.6 v. r = 1.0 k , c = 50 pf* 2 0 100 khz (repeat) [start] condition hold time sda scl t hdsta 4.0 ? s scl clock ?l? width t low 4.7 ? s scl clock ?h? width t high 4.0 ? s repeat [start] condition setup time scl sda t susta 4.7 ? s data hold time scl sda t hddat 03.45* 3 s data setup time sda scl t sudat power-supply voltage of external pull-up resistor at 5.0 v. f cp * 1 20 mhz, r = 1.2 k , c = 50 pf* 2 power-supply voltage of external pull-up resistor at 3.6 v. f cp * 1 20 mhz, r = 1.0 k , c = 50 pf* 2 250* 4 ? ns power-supply voltage of external pull-up resistor at 5.0 v. f cp * 1 > 20 mhz, r = 1.2 k , c = 50 pf* 2 power-supply voltage of external pull-up resistor at 3.6 v. f cp * 1 > 20 mhz, r = 1.0 k , c = 50 pf* 2 200* 4 ? [stop] condition setup time scl sda t susto power-supply voltage of external pull-up resistor at 5.0 v. r = 1.2 k , c = 50 pf* 2 power-supply voltage of external pull-up resistor at 3.6 v. r = 1.0 k , c = 50 pf* 2 4.0 ? s bus free time between [stop] condition and [start] condition t bus 4.7 ? s
mb90330a series ds07-13734-9e 51 note : the rating of the in put data set-up time in the device connecte d to the bus cannot be satisfied depending on the load capacitance or pull-up resist or. be sure to adjust the pull-up re sistor of sda and scl if the rating of the input data set-up time cannot be satisfied. sda scl 6 tcp ? note of sda, scl set-up time input data set-up time sda scl t low t hdsta t hddat t sudat t susta t susto t hdsta t high t bus ? timing definition
mb90330a series 52 ds07-13734-9e (7) timer input timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : t cp : refer to ? (1) clock input timing?. (8) timer output timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) (9) trigger input timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : t cp : refer to ? (1) clock input timing?. parameter symbol pin name conditions value unit min max input pulse width t tiwh t tiwl frck, inx, tinx, pwc ? 4 t cp ? ns parameter symbol pin name conditions value unit min max clk t out change time ppg0 to ppg5 change time out0 to out3 change time t to totx, ppgx, outx ? 30 ? ns parameter symbol pin name conditions value unit remarks min max input pulse width t trgh t trgl intx, adtg ? 5 t cp ? ns at normal operating 1 ? s in stop mode 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl pwc tinx inx frck clk ppgx outx 2.4 v t to 2.4 v 0.8 v 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl intx adtg
mb90330a series ds07-13734-9e 53 (10) bus read timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) note : t cp : refer to ? (1) clock input timing?. parameter sym- bol pin name conditions value unit remarks min max ale pulse width t lhll ale ? t cp / 2 ? 15 ? ns at f cp = 24 mhz t cp / 2 ? 20 ? ns at f cp = 12 mhz t cp / 2 ? 35 ? ns at f cp = 6 mhz valid address ale time t avll address, ale ? t cp / 2 ? 17 ? ns t cp / 2 ? 40 ? ns at f cp = 6 mhz ale address valid time t llax ale, address ? t cp / 2 ? 15 ? ns valid address rd time t avrl rd , address ? t cp ? 25 ? ns valid address valid data input t avdv address/ data ? ? 5 t cp / 2 ? 55 ns ? 5 t cp / 2 ? 80 ns at f cp = 6 mhz rd pulse width t rlrh rd ? 3 t cp / 2 ? 25 ? ns at f cp = 24 mhz 3 t cp / 2 ? 20 ? ns at f cp = 12 mhz rd valid data input t rldv rd , data ? ? 3 t cp / 2 ? 55 ns ? 3 t cp / 2 ? 80 ns at f cp = 6 mhz rd data hold time t rhdx rd , data ? 0 ? ns rd ale time t rhlh rd , ale ? t cp / 2 ? 15 ? ns rd address valid time t rhax address, rd ? t cp / 2 ? 10 ? ns valid address clk time t avch address, clk ? t cp / 2 ? 17 ? ns rd clk time t rlch rd , clk ? t cp / 2 ? 17 ? ns ale rd time t llrl rd , ale ? t cp / 2 ? 15 ? ns
mb90330a series 54 ds07-13734-9e 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc clk ale rd a23 to a16 ad15 to ad00 2.4 v t avch t lhll t rhlh t avll t avrl t rldv t rlrh t rhax t rhdx t llax t llrl t rlch t avdv 0.8 v 2.4 v 0.8 v 2.4 v 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc a23 to a00 d15 to d00 t rldv t rhax t rhdx t avdv 0.8 v 2.4 v address read data read data in multiplex mode in non-multiplex mode
mb90330a series ds07-13734-9e 55 (11) bus write timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) note : t cp : refer to ? (1) clock input timing?. parameter symbol pin name conditions value unit remarks min max valid address wr time t avwl address, wr ? t cp ? 15 ? ns wr pulse width t wlwh wrl , wrh ? 3 t cp / 2 ? 25 ? ns at f cp = 24 mhz ? 3 t cp / 2 ? 20 ? ns at f cp = 12 mhz valid data output wr time t dvwh data, wr ? 3 t cp / 2 ? 15 ? ns wr data hold time t whdx wr , data ? 10 ? ns at f cp = 24 mhz ? 20 ? ns at f cp = 12 mhz ? 30 ? ns at f cp = 6 mhz wr address valid time t whax wr , address ? t cp / 2 ? 10 ? ns wr ale time t whlh wr , ale ? t cp / 2 ? 15 ? ns wr clk time t wlch wr , clk ? t cp / 2 ? 17 ? ns wr (wrl, wrh) 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v clk ale a23 to a16 ad15 to ad00 t whlh t avwl t dvwh t dvwh t wlwh t whax t whdx t wlch 0.8 v 2.4 v 0.8 v 2.4 v a23 to a00 d15 to d00 t whax t whdx 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v address write data write data in multiplex mode in non-multiplex mode
mb90330a series 56 ds07-13734-9e (12) ready input timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) parameter symbol pin name conditions value unit remarks min max rdy set-up time t ryhs rdy ? 35 ? ns ? 70 ? ns f cp = 6 mhz rdy hold time t ryhh ? 0 ? ns t ryhh 2.4 v 2.4 v 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc clk ale rd/wr t ryhs t ryhs rdy wait applies (1cycle) rdy wait not applied
mb90330a series ds07-13734-9e 57 (13) hold timing (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) notes : ? it takes one cycle or more for hak to change after the hrq pin is captured. ? t cp : refer to ? (1) clock input timing?. parameter symbol pin name conditions value unit min max pin floating hak time t xhal hak ? 30 t cp ns hak pin valid time t hahv hak t cp 2 t cp ns hak t xhal t hahv 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v each pin high-z
mb90330a series 58 ds07-13734-9e 5. electrical characteristics for the a/d converter (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : t cp : refer to ? 4. ac characteristics (1) clock input timing?. *2 : the current when the cpu is in stop mode and the a/d conv erter is not operating (for v cc = av cc = avrh = 3.3 v). parameter sym- bol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb nonlinear error ?? ? ? 2.5 lsb differential linear error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an15 av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb v 1 lsb = (avrh ? av ss )/1024 full-scale transition voltage v fst an0 to an15 avrh ? 3.5 lsb avrh ? 1.5 lsb avrh + 0.5 lsb v conversion time ?? ? 176 t cp *1 ? ns sampling time ?? ? 64 t cp *1 ? ns analog port input current i ain an0 to an15 ?? 10 a analog input voltage v ain an0 to an15 0 ? avrh v reference voltage ? avrh 2.7 ? av cc v power supply current i a av cc ? 1.4 3.5 ma i ah av cc ?? 5 a*2 reference voltage supplying current i r avrh ? 95 170 a i rh avrh ?? 5 a*2 interchannel disparity ? an0 to an15 ?? 4lsb
mb90330a series ds07-13734-9e 59 notes : ? about the external impedance of th e analog input and its sampling time ? a/d converter with sample and hold ci rcuit. if the external impedance is to o high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. ? to satisfy the a/d conversion precision standard, co nsider the relationship between the external impedance and minimum sampling time and eit her adjust the resistor value and operating frequency or decrease the external impedance so that the sampling ti me is longer than the minimum value. ? if the sampling time cannot be suffic ient, connect a capacitor of about 0.1 f to the analog input pin. ? about errors as | avrh | becomes smaller, values of relative errors grow larger. r c analog input comparator ? analog input circuit model during sampling : on note : the values are reference values. mb90333a mb90f334a mb90f335a MB90V330A r 1.9 k (max) 1.9 k (max) 1.9 k (max) 1.9 k (max) c 32.3 pf (max) 25.0 pf (max) 25.0 pf (max) 32.3 pf (max) 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 mb90333a/ MB90V330A mb90f334a mb90f335a 20 18 16 14 12 10 8 6 4 2 0 0123456 8 7 mb90333a/ MB90V330A mb90f334a mb90f335a (external impedance = 0 k to 100 k ) external impedance [k ] minimum sampling time [ s] (external impedance = 0 k to 20 k ) external impedance [k ] minimum sampling time [ s] ? the relationship between the external impedance and minimum sampling time
mb90330a series 60 ds07-13734-9e a/d converter glossary (continued) resolution : analog changes that are id entifiable with the a/d converter. linearity error : the deviation of the straig ht line connecting the zero transition point (?00 0000 0000? ? ?00 0000 0001?) with the full-scale transition point (?11 1111 1110? ? ?11 1111 1111?) from actual conversion characteristics. differential linearity error : the deviation of input vo ltage needed to change the output code by 1 lsb from the theoretical value. total error : the total error is defined as a diff erence between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh v nt 0.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} act u al conversion val u e (meas u red val u e) act u al conversion val u e theoretical characteristics digital o u tp u t analog inp u t total error total error for digital output n = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb (theoretical value) = avrh ? avss 1024 [v] v ot (theoretical value) = avss + 0.5 lsb [v] v fst (theoretical value) = avrh ? 1.5 lsb [v] v nt : voltage at a transition of digi tal output from (n - 1) to n
mb90330a series ds07-13734-9e 61 (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh v ot (meas u red val u e) {1 lsb (n ? 1) + v ot } act u al conversion val u e v fst (meas u red val u e) v nt (meas u red val u e) act u al conversion val u e theoretical characteristics digital o u tp u t digital o u tp u t analog inp u t av ss avrh n + 1 n n ? 1 n ? 2 act u al conversion val u e act u al conversion val u e theoretical characteristics analog inp u t v nt (meas u red val u e) v (n + 1) t (meas u red val u e) linearity error differential linearity error linearity error of digital output n v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] = differential linearity error of digital output n v ( n + 1 ) t ? v nt 1 lsb ? 1 [lsb] = v fst ? v ot 1022 [v] 1 lsb = v ot : voltage at transition of digital output from ?000 h ? to ?001 h ? v fst : voltage at transition of digital output from ?3fe h ? to ?3ff h ?
mb90330a series 62 ds07-13734-9e 6. usb characteristics (v cc = av cc = 3.3 v 0.3 v, v ss = av ss = 0.0 v, t a = 0 c to + 70 c) * : arrange the series resistance r s values in order to set the impedance value within the output impedance zsrv. ? data signal timing (full speed) ? data signal timing (low speed) parameter sym- bol value unit remarks min max input characteristics input high level voltage v ih 2.0 ? v input low level voltage v il ? 0.8 v differential input sensitivity v di 0.2 ? v differential common mode range v cm 0.8 2.5 v output characteristics output high level voltage v oh 2.8 3.6 v i oh = ? 200 a output low level voltage v ol 0.0 0.3 v i ol = 2 ma cross over voltage v crs 1.3 2.0 v rise time t fr 4 20 ns full speed t lr 75 300 ns low speed fall time t ff 4 20 ns full speed t lf 75 300 ns low speed rising/falling time matching t rfm 90 111.11 % (t fr /t ff ) t rlm 80 125 % (t lr /t lf ) output impedance z drv 28 44 including rs = 27 series resistance r s 25 30 recommended value = 27 at using usb* dvp/hvp dvm/hvm 90% t fr 10% 90% 10% t ff vcrs rise time fall time hvp hvm 90% t lr 10% 90% 10% tlf vcrs rise time fall time
mb90330a series ds07-13734-9e 63 ? load condition (full speed) ? load condition (low speed) dvp/hvp r s = 27 c l = 50 pf dvm/hvm r s = 27 z usb z usb c l = 50 pf testing point testing point hvp r s = 27 c l = 50 pf to 150 pf hvm r s = 27 c l = 50 pf to 150 pf z usb z usb testing point testing point
mb90330a series 64 ds07-13734-9e 7. flash memory write/erase characteristics * : this value comes from the technology qualification. (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) parameter condition value unit remarks min typ max sector erase time t a = + 25 c v cc = 3.0 v ? 115s excludes 00 h programming prior to erasure. chip erase time ? 9 ? s *:mb90f334a (384 kbytes) excludes 00 h programming prior to erasure. ? 14 ? *:mb90f335a (512 kbytes) excludes 00 h programming prior to erasure. word (16-bit width) programming time ? 16 3600 s except for over head time of system level programming/erase cycle ? 10000 ?? cycle flash memory data retaining period average t a = + 85 c 20 ?? year *
mb90330a series ds07-13734-9e 65 ordering information part number package remarks mb90f334apmc1 mb90f335apmc1 mb90333apmc1 120-pin plastic lqfp (fpt-120p-m24) mb90f334apmc mb90f335apmc mb90333apmc 120-pin plastic lqfp (fpt-120p-m21) MB90V330Acr 299-pin ceramic pga (pga-299c-a01) for evaluation
mb90330a series 66 ds07-13734-9e package dimensions please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ (continued) 120-pin plastic lqfp lead pitch 0.40 mm package w idth package length 14.0 mm 14.0 mm lead shape g u ll w ing sealing method plastic mold mo u nting height 1.70 mm max code (reference) p-lfqfp120-14 14-0.40 120-pin plastic lqfp (fpt-120p-m24) (fpt-120p-m24) c 2006-2010 fujitsu semico n ductor limited f120036s-c-1-3 0.07(.003) m i n dex 16.000.20(.630.00 8 )sq 130 31 60 91 120 61 90 lead n o. (stand off) 0.100.10 (.004.004) 0.25(.010) (.024.006) 0.600.15 (.020.00 8 ) 0.500.20 (mo u nting height) 0~ 8 details of "a" part 1.50 +0.20 ?0.10 +.00 8 ?.004 .059 "a" 0.40(.016) 0.160.05 (.006.002) 0.1450.055 (.006.002) 0.0 8 (.003) * 14.000.10(.551.004)sq dimensions in mm (inches). n ote: the v al u es in parentheses are reference v al u es. n ote 1) * : these dimensions do not incl u de resin protr u sion. n ote 2) pins w idth and pins thickness incl u de plating thickness. n ote 3) pins w idth do not incl u de tie b ar c u tting remainder.
mb90330a series ds07-13734-9e 67 (continued) please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ 120-pin plastic lqfp lead pitch 0.50 mm package w idth package length 16.0 16.0 mm lead shape g u ll w ing sealing method plastic mold mo u nting height 1.70 mm max w eight 0. 88 g code (reference) p-lfqfp120-16 16-0.50 120-pin plastic lqfp (fpt-120p-m21) (fpt-120p-m21) c 2002-2010 fujitsu semico n ductor limited f120033s-c-4-7 130 60 31 90 61 120 91 sq 1 8 .000.20(.709.00 8 )sq 0.50(.020) 0.220.05 (.009.002) m 0.0 8 (.003) i n dex .006 ?.001 +.002 ?0.03 +0.05 0.145 "a" 0.0 8 (.003) lead n o. .059 ?.004 +.00 8 ?0.10 +0.20 1.50 details of "a" part (mo u nting height) 0.600.15 (.024.006) 0.25(.010) (.004.002) 0.100.05 (stand off) 0~ 8 * .630 ?.004 +.016 ?0.10 +0.40 16.00 dimensions in mm (inches). n ote: the v al u es in parentheses are reference v al u es. n ote 1) * : these dimensions do not incl u de resin protr u sion. resin protr u sion is +0.25(.010) max(each side). n ote 2) pins w idth and pins thickness incl u de plating thickness. n ote 3) pins w idth do not incl u de tie b ar c u tting remainder.
mb90330a series 68 ds07-13734-9e main changes in this edition the vertical lines marked in the left side of the page show the changes. page section change results 39 electrical characteristics 2. recommended operating condi- tions corrected the remarks for operating temperature as follows; when using usb when using usb, at external bus opera- tion
mb90330a series ds07-13734-9e 69 memo
mb90330a series 70 ds07-13734-9e memo
mb90330a series ds07-13734-9e 71 memo
mb90330a series fujitsu semiconductor limited nomura fudosan shin-yokohama bldg . 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu semiconductor america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://us.fujitsu.com/micro/ europe fujitsu semiconductor europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/semiconductor/ korea fujitsu semiconductor korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu semiconductor asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ fujitsu semiconductor shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fa x : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu semiconductor pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of f unction and application circuit examples, in this document are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use base d on such information. when you develop equipment incorporating the device based on such information, you must assume any responsi bility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of f unction and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringe ment of any third-party's intellectual property right or othe r right by using such information. fujitsu semiconductor assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would re sult from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers th at, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to d eath, personal injury, severe physical damage or other loss (i.e., nuclear reaction con trol in nuclear facility, aircraft flight control, air tr affic control, mass transport control, me dical life support system, missile launch con trol in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu semiconductor will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety design measures into your facility and equi pment such as redundancy, fire protection, and prevention of ov er-current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

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